1. Field of the Invention
The present invention relates to a level converter, and more particularly to a level converter for converting an input signal of the ECL rating logic level into an output signal of the MIS or BiMIS rating logic level.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows a conventional level converter.
As shown in FIG. 1, the conventional level converter has ECL circuit 10 comprising a pair of bipolar transistors Q11, Q12 whose emitters are coupled to each other, load resistors R1, R2 connected to respective bipolar transistors Qll, Q12, and constant-current supply 11. When data D11, D12 are supplied respectively to the bases of bipolar transistors Qll, Q12, the collectors thereof output respective data D01, D02 of the ECL logic level.
The level converter also has a pair of emitter followers 20c, 20d each having bipolar transistor Q21 and constant-current supply 21. When data D01, D02 are supplied to the respective bases of bipolar transistors Q21 of emitter followers 20c, 20d, they output respective signals IN1, IN2.
The level converter also includes a pair of level converting circuits 30A, 30B each having a pair of P-type MIS transistors M31, M33 and a pair of N-type MIS transistors M32, M34. When signals IN1, IN2 are supplied to level converting circuits 30A, 30B, they convert supplied signals IN1, IN2 into respective MIS or BiMIS logic level signals.
The level converter further has a pair of drivers 40a, 40b each having P-type MIS transistor M41, N-type MIS transistors M42, M43 and bipolar transistor Q41. When drivers 40a, 40b are supplied with the respective signals from level converting circuits 30A, 30B, drivers 40a, 40b produce output signals OUT1, OUT2, respectively, to drive a logic circuit (not shown).
The output signals from level converting circuits 30A, 30B are of the MIS or BiMIS logic level, as described above. Each of level converting circuits 30A, 30b has an output stage composed of MIS transistors M33, M34. If a large load is directly driven by these MIS transistors, then the signals from the transistors are transmitted with a large time delay. Therefore, BiMIS drivers 40a, 40b are connected to the output terminals of level converting circuits 30A, 30B for driving the load. In this case, constant currents flow through level converting circuits 30A, 30B.
Since the output stage of each of level converting circuits 30A, 30B is composed of MIS transistors M33, M34 and also since BiMIS drivers 40a, 40b are required to drive a large load, as described above, the time delay which the input signals undergo is still large. In addition, the steady currents flowing through level converting circuits 30A, 30B result in a large current consumption.
FIG. 2 of the accompanying drawings illustrates a modified circuit of the conventional level converting circuits 30A, 30B. Reference voltage V.sub.REF is applied to the gate of P-type MIS transistor M33 so that MIS transistor M33 is turned off when the input signal applied thereto is low. With the circuit arrangement shown in FIG. 2, while the time delay that the input signal suffers is small, a large current flows through the level converting circuit depending on reference voltage V.sub.REF and because of current-mirror N-type MIS transistor M32, with a resulting large power consumption. Since the level converting circuit shown in FIG. 2 is also low in driving capability, it is necessary to add a driver for higher driving capability if a large load is coupled thereto.